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copyright copyright ? 2009 cognivue corporation ("cognivue") all rights reserved. this document contains information which is proprietary to cognivue and may be used for non-commercial purposes within your org anization in support of cognivue?s products. no other use or transmission of all or any part of this document is permitted without written permission from cognivue, and must include all copyright and other proprietary notices. use or transmission of all or any part of this documen t in violation of any applicable canadian or other legislation is hereby expressly prohibited. user obtains no rights in the information or in any product, proc ess, technology or trademark which it includes or describes, a nd is expressly prohibited from modifying the information or creating derivat ive works without the express written consent of cognivue. disclaimer cognivue assumes no responsibility for the accuracy or complet eness of the information presented which is subject to change wit hout notice. in no event will cognivue be liable for any direct, indirect, special, incidental or consequential damages, including lost profits, l ost business or lost data, resulting from the use of or reliance upon the information, w hether or not cognivue has been advised of the possibility of such damages. mention of non-cognivue products or services is for informati on purposes only and constitutes neither an endorsement nor a reco mmendation. cv220x datasheet ds-10163-00-01 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 2/69 revision history version details of change author date 01 initial release tina jeffrey dec 14, 2009 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 3/69 table of contents 1 introduc tion................................................................................................................... ............................... 8 1.1 cv220x f eatur es ................................................................................................................ .................. 10 1.1.1 cv220x general feat ures........................................................................................................ .... 10 1.1.2 video proc essi ng ............................................................................................................... ........... 10 1.1.3 digital still im age proce ssing................................................................................................. ....... 11 1.1.4 audio proc essing ............................................................................................................... ........... 12 1.1.5 graphi cs ....................................................................................................................... ................. 13 1.1.6 image sensor interf ace ......................................................................................................... ........ 13 1.1.7 display c ontrolle r ............................................................................................................. ............. 13 1.1.8 usb 2.0 high speed controller ................................................................................................. 13 1.1.9 entropy codec.................................................................................................................. ............. 13 1.1.10 integrated memo ry .............................................................................................................. .......... 14 1.1.11 audio inte rface ................................................................................................................ .............. 14 1.1.12 media storage interf ace ........................................................................................................ ........ 14 1.1.13 serial in terfac es .............................................................................................................. .............. 14 1.1.14 mpeg-2 transport st ream inte rface ............................................................................................ 14 1.1.15 smart card interface ........................................................................................................... .......... 14 1.1.16 other inte rfaces............................................................................................................... .............. 14 1.2 reference i nput cl ock .......................................................................................................... ................. 15 1.3 boot-up options ................................................................................................................ .................... 15 1.4 package ........................................................................................................................ ......................... 15 1.5 power s upply ................................................................................................................... ...................... 15 1.6 ambient operati ng temper ature .................................................................................................. ......... 15 2 system design c onsiderat ions ................................................................................................... .............. 16 2.1 cv220x boot-up and configur ation............................................................................................... ....... 16 2.2 boot-up ti meline ............................................................................................................... .................... 18 2.3 boot load modes ................................................................................................................ ................... 18 2.4 low power conf igurat ions ....................................................................................................... .............. 19 2.5 reset.......................................................................................................................... ............................ 20 3 hardware ar chitec ture.......................................................................................................... ..................... 22 3.1 peripher als .................................................................................................................... ......................... 23 3.1.1 sensor in terface ............................................................................................................... ............. 23 3.1.2 keypad scan in terface.......................................................................................................... ........ 24 3.1.3 system memo ry .................................................................................................................. .......... 26 3.1.4 nand flash in terface ........................................................................................................... ........ 26 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 4/69 3.1.5 display interface po rt and tv output ........................................................................................... 27 3.1.6 mpeg2 transport inte rface (m p2ts)........................................................................................... 30 3.1.7 usb 2.0 hi gh speed............................................................................................................. ..... 31 3.1.8 smart card interface ........................................................................................................... .......... 33 3.1.9 serial in terfac es .............................................................................................................. .............. 34 3.1.9.1 uart.......................................................................................................................... 34 3.1.9.2 spi............................................................................................................................ .. 35 3.1.10 gps inteface ................................................................................................................... .............. 36 3.1.11 audio inte rface ................................................................................................................ .............. 37 3.1.12 media storage (sd/s dhc) ........................................................................................................ ... 38 3.1.13 i 2 c interf ace.................................................................................................................... ............... 39 3.1.14 mmcplus in terface.............................................................................................................. .......... 39 3.1.15 external memory interf ace ...................................................................................................... ...... 40 3.1.16 pulse width modul ated outputs.................................................................................................. .. 42 3.1.17 power management interf ace ..................................................................................................... .. 42 3.1.18 gpios and alter nate func tions .................................................................................................. .. 43 3.1.19 production test and system signals ............................................................................................ 45 3.1.20 core and i/o power............................................................................................................. .......... 46 3.2 pll and timing generat ion ...................................................................................................... ............. 47 4 packaging...................................................................................................................... ............................ 48 4.1 CV2201 ......................................................................................................................... ......................... 48 4.2 cv2202 ......................................................................................................................... ......................... 49 4.3 cv2203 ......................................................................................................................... ......................... 50 4.4 cv220x pinout.................................................................................................................. ..................... 51 5 electrical s pecificat ions...................................................................................................... ....................... 60 5.1 absolute maxi mum ra ting ........................................................................................................ ............. 60 5.2 recommended oper ating ranges ................................................................................................... ..... 60 5.3 dc characte ristics ............................................................................................................. .................... 61 5.4 ac specif icati ons .............................................................................................................. ..................... 62 6 ordering info rmation ........................................................................................................... ...................... 69 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 5/69 table of figures figure 1: cv220x based pers onal media play er/rec order .......................................................................... ........ 9 figure 2: boot-up sequence ti meline............................................................................................ .................... 18 figure 3: power-up re set timing waveform ....................................................................................... .............. 20 figure 4: reset architecture ................................................................................................... ............................ 21 figure 5: cv220x hard ware arch itecture......................................................................................... .................. 22 figure 6: keyscan syst em implem entation ........................................................................................ ................ 25 figure 7: nand fl ash connec tivity .............................................................................................. ...................... 27 figure 8: cpu-type lcd and tv connect ed to dip (using internal dac) ....................................................... 28 figure 9: dbi to cpu-type display wavefo rm di agram ............................................................................. ........ 29 figure 10: mp2ts interf ace signal formats...................................................................................... ................. 31 figure 11: usb/ho st connec tivity............................................................................................... ........................ 32 figure 12: smart ca rd connec tivity ............................................................................................. ....................... 33 figure 13: gps interf ace ....................................................................................................... ............................. 36 figure 14: audi o interf ace..................................................................................................... .............................. 37 figure 15: media storage in terface to sd card.................................................................................. ................ 39 figure 16: cv2202 interface to external memory................................................................................. .............. 41 figure 17: crystal connected to cv220x......................................................................................... .................. 47 figure 18: cv 2201 pack age ...................................................................................................... ......................... 48 figure 19: cv 2202 pack age ...................................................................................................... ......................... 49 figure 20: cv 2203 pack age ...................................................................................................... ......................... 50 figure 21: re set timing........................................................................................................ .............................. 65 figure 22: input clock ti ming .................................................................................................. ........................... 65 figure 23: sensor interface timing............................................................................................. ........................ 65 figure 24: dip port ti ming..................................................................................................... ............................. 65 figure 25: spi port ti ming..................................................................................................... ............................. 66 figure 26: audio port timing ................................................................................................... ........................... 66 figure 27: sd/mmc port timing .................................................................................................. ....................... 67 figure 28: mp2ts in terface timing .............................................................................................. ...................... 67 figure 29: i2c port ti ming ..................................................................................................... ............................. 67 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 6/69 figure 30: mmcplus port timing ................................................................................................. ....................... 68 figure 31: gps in terface timing................................................................................................ ......................... 68 figure 32: pmi port ti ming ..................................................................................................... ............................ 68 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 7/69 table of tables table 2-1: cv220x boot-u p configurabl e opti ons ................................................................................. ........... 17 table 2-2: configuring boot load using dip_dat a[5:3] pins...................................................................... ......... 19 table 3-1: sensor inte rface exter nal pinout .................................................................................... ................... 24 table 3-2: key scan interface ................................................................................................... ........................... 25 table 3-3: cv220x system me mory configuf igurat ions ............................................................................. ....... 26 table 3-4: nand fl ash inte rface ................................................................................................ ........................ 27 table 3-5: disp lay interface ................................................................................................... ............................. 30 table 3-6: mp2t s interf ace ..................................................................................................... ........................... 31 table 3-7: u sb interf ace....................................................................................................... .............................. 32 table 3-8: smart card inte rface................................................................................................ .......................... 34 table 3-9: uart interf ace ...................................................................................................... ............................ 35 table 3-10: spi signals ........................................................................................................ .............................. 36 table 3-11: g ps interf ace ...................................................................................................... ............................ 37 table 3-12: audi o interface.................................................................................................... ............................. 38 table 3-13: media storage inte rface ............................................................................................ ...................... 39 table 3-14: i2 c interf ace ...................................................................................................... .............................. 39 table 3-15: mmcplus interf ace pinout for CV2201, cv2202........................................................................ ..... 40 table 3-16: cv2202 exte rnal memo ry pinout ...................................................................................... .............. 42 table 3-17: pwm function pinout ................................................................................................ ...................... 42 table 3-18: pmi function pinout................................................................................................ ......................... 43 table 3-19: gpios and alternate func tions shared with external pins ............................................................ 45 table 3-20: production te st and system signals................................................................................. .............. 46 table 3-21: cv220x power supply ................................................................................................ .................... 47 table 4-1: cv220x pinout ....................................................................................................... ........................... 58 table 4-2: cv220x power pin .................................................................................................... ........................ 59 table 5-1: cv220x abso lute maximu m rating ...................................................................................... ............ 60 table 5-2: cv220x reco mmended operat ing r ange .................................................................................. ..... 61 table 5-3: cv220x dc characteri stics ........................................................................................... ................... 62 table 5-4: cv220x ac specific ations ............................................................................................ .................... 64 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 8/69 1 introduction the cv220x is a family of highly-programmable image cognition processors (icp) designed to enable programmable imaging and video applications for automotiv e smart cameras, internet protocol (ip) video surveillance cameras and converged consumer devices such as personal media players (pmp). cognivue icps belonging to the cv220x family are programmabl e system-on-chip (soc) devices powered by the apex? technology and include: ? CV2201 ? equipped with 128mbit of sta cked mobile ddr sdram in package; ? cv2202 ? capable of interfacing to external ddr sdram up to 1gbit in size; ? cv2203 ? system in package (sip) with 1gbi t mlc nand flash and 128mbit mobile ddr sdram stacked in package; this device has variants qualified for industrial and automotive standards; automotive qualified parts conform to aec-q100; these icps offer high performance programmable platfo rm solutions while providing developers with a low power, extremely flexible device for full-featured imaging and video applications including mobile tv for converged applications such as personal media play ers (pmps) and imaging and video analytics for use in smart cameras for ensuring driver safety and enhancing se curity. these target applications may benefit from the following feature set: ? all video codec standards support d1 resoluti on at 30fps (see section 1.1.2 for details) ? video/audio player with dual mpeg2 transport str eam interfaces supporti ng dvb-h/t and atsc-m/h channels for picture-in-picture ? digital still image capture supporting sensors up to 12 mpixels ? tv output (ntsc/pal) via cable or bluetooth with tv encoder dac on chip ? support for all new algorithms (proprieta ry or standard) with software changes only ? picture viewer with image editing options ? video editing, vod, video-telephony (vt) , multimedia messaging service (mms) ? wm-drm, oma-drm, divx-drm ready ? support for compute-intensive multi-tasking operati ons such as handling video ring tone while watching dvb-h/t pip ? video editing ? transcoding ? integrated security and cryptographic support feat ures for digital rights, content protection and subscription services ? multiple power domains allow for low power operation free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 9/69 ? usb 2.0 high speed interface including phy on chip ? sd/sdhc, mmc plus and nand flash interface ? small form factor for stacked or external memory figure 1 shows a typical confi guration of the cv220x icp. dac/adc s/t-dmb/dvb-h baseband 1 77 77 77 088 john doe stacked or external nand flash sd/sdhc and mmc plus cmos/ccd yuv 8-bit quad buffer lcds 8/16/18-bit or vga rgb lcd analog ntsc/pal usb device (e.g. pc) keypad figure 1: cv220x based personal media player/recorder free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 10/69 1.1 cv220x features 1.1.1 cv220x general features ? dual arm926ej-s? risc processor eac h with 16 kb i-cache and 16 kb d-cache ? high performance apex? dsp sub-system technol ogy based on patented simd parallel processing architecture ? integrated jazelle java hardware accelerator ? integrated usb 2.0 high speed controller ? sensor interface supports 10-bit yuv datapath providing up to 12 mpixel resolution ? integrated image enhancement func tions in sensor interface ? dual mp2ts interfaces for us e with mobile tv applications ? multiple power domains and voltage islands to support low power modes ? dma controller for memory-to-memory, memory-t o-peripheral, peripheral-to-memory, and peripheral- to-peripheral data transfer ? digital output supporting up to 24 bits with external video dac ? integrated 10-bit dac for analog composite video output to tv ? dual lcd module ? data security and pay-per-view features: ? hardware acceleration for oma-2 cryptographic operations ? secure boot mode ? smart card interface ? sd/sdhc interface ? mmc plus interface ? nand flash interface 1.1.2 video processing ? fully-programmable array processor for running video processing algorithms ? video codecs support diverse resolutions at 30fps with 4 mbps maximum bitrate ? supports wide cam (768 x 432) encoding at 30fps free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 11/69 ? supports slow motion (eg. 1/5th at 30fps) ? supported video decoding standards: ? mpeg-4 simple profile and advanced si mple profile supports d1 at 30fps ? h.263 baseline, profile 3 supports d1 at 30fps ? divx (v5.0/6.0) with drm supports d1 at 30fps ? xvid supports d1 at 30fps ? mpeg2 support d1 at 30fps ? wmv (vc-1) with drm supports d1 at 30fps ? h.264 supports d1 at 30fps ? rv supports d1 at 30fps ? rmvb supports d1 at 30fps ? vp6 supports d1 at 30fps ? supported video encoding standards: ? mpeg-4 simple profile supports d1 at 30fps or qvga at 120fps ? h.263 baseline profile supports d1 at 30fps ? divx/xvid avi support d1 at 30fps ? all new codec standards may be supported with sw change only ? supports video streaming and progressive download ? supports full motion estimation and variable pixel search region ? supports constant and variable bit rate (cbr and vbr) ? real-time viewfinder on lcd and tv with scaling, rotation, mirroring and flipping transformations ? supports special effects: black and white, s epia, negative, cool, hot, sketch, emboss and others 1.1.3 digital still image processing ? captures still images up to 12 mpix els using image sensor with isp ? supports image processing and editing ? compression and decompression in accordance with iso/iec 10918 jpeg standard free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 12/69 ? supports jpeg capture on-the-fly ? support for common decompression st andards: tiff, gif, png and wbmp ? supports exchangeable image file (exif) format ? programmable quantization and huffman tables and high, medium and low compression quality settings ? real-time viewfinder on lcd and tv with scaling, rotation, mirroring and flipping transformations ? supports special effects: b&w, sepia, negative, cool, hot, sketch, emboss and others ? image scaling and window of interest ? supports continuous digital zoom (including true upscaling) up to 2x ? supports decorative frame overlay and photo captioning ? thumbnail browser and file management 1.1.4 audio processing ? audio encoding compliant with the followi ng standards: aac, mp3, amr-nb, g.723.1, wav ? audio decoding compliant with the following standards: aac, aac+, eaac+, mp3, bsac, wma, wma10 pro, ra, amr-nb, amr-wb, g.723.1, wav, ogg ? supports mtp and music player db ? all other codec standards may be supported with sw change only ? midi synthesis of up to 128 voices at 48 khz for melody ring tones supporting wide range of midi files including: ? .mid midi file format ? .rtx extended ringtone format ? .sms sms ringtone ? .xmf extensible music format (midi + digitally recorded music) ? .mxmf mobile version of .xmf ? .mmf smaf ringtone format ? .rmf rich music format ? .imy imelody ringtone format free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 13/69 ? directly connects to i2s or ac97 compliant audio device 1.1.5 graphics ? true-colour (24 bits per pixel) processing ? 2d graphics functions including: bitblt, solid fill, overlay, pixel-based alpha-blending, rotation, scaling, colour space conversion, colour depth expansion and reduction 1.1.6 image sensor interface ? supports yuv up to 12 mpixel s, 10-bit parallel interface ? supports scale-down (vertical and horizontal) ? performs image enhancement functions including: edge, image, grey scale, sepia, negative, emboss and sketch 1.1.7 display controller ? supports up to four cpu-like dev ices (for example dual 8/9/16/ 18-bit lcd modules and two other devices with cpu-like interfaces) concurrently with tv out, or s upport rgb-24 master timing interface up to xga resolution ? itu-r 601/656 compatible digital video output ? on-chip composite video encoder compatible with pal/ntsc/ntsc-japan video modulation standards ? integrated high quality 10-bit video dac for direct connection to tv 1.1.8 usb 2.0 high speed controller ? usb 2.0 high speed compliant ? usb 2.0 phy integrated on-chip ? supports mass storage device 1.1.9 entropy codec ? hardware accelerated entropy encoding (mpeg-4 , h.263, jpeg) and decoding (mpeg-4, h.263, divx, vc-1,h.264, rv) blocks ? programmable huffman tables and zigzag modes ? embedded bit packing and unpacking blocks for automated file/video stream generation ? direct connection with array processor for efficient data transfer free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 14/69 1.1.10 integrated memory ? CV2201 has 128 mbit ddr sdram integrated in package ? cv2202 has no internal memory but is capable of inte rfacing to external sdram up to 1gbit in size ? cv2203 has 128 mbit ddr sdram and 1gbi t nand flash integrated in package 1.1.11 audio interface ? i2s and ac97 compliant audio interface 1.1.12 media storage interface ? supports sd/sdhc removable memory cards ? supports mmc plus memory card ? supports 8-bit nand flash devices ? supports fat-16 and fat-32 file system with long name support and international characters 1.1.13 serial interfaces ? two uart interfaces and two spis 1.1.14 mpeg-2 transport stream interface ? dual interfaces to dmb baseband to receive mpeg2 transport streams 1.1.15 smart card interface ? complies with integrated circuit card spec ifications: iso/iec 7816-3 amendment i (2002-06-01); iso/iec 7816-10; emv book 1 version 4.1 (2004-05-01) 1.1.16 other interfaces ? general purpose i/o (gpio) ? selectable as alte rnative functions for various interface pins ? two pwm (pulse width modulated) output s with programmable frequency and duty cycle ? jtag test and debugging interface for arms free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 15/69 1.2 reference input clock ? programmable internal clock frequencies ? input clocks: ? 10-30 mhz ? 5 on-chip plls generate clocks for system, array pr ocessor, display interface, other interfaces and memory ? clocks supplied by either a crystal or oscillator 1.3 boot-up options ? code resident in nand flash accessible via spi or nand interface 1.4 package ? CV2201 is available in a 9 x 9mm bga package, with 236 balls ? cv2202 is available in a 10 x 10mm bga package with 296 balls ? cv2203 is available in a 10 x 10 mm bga package, with 196 balls 1.5 power supply ? 1.0 v core and 1.8/2.8 v i/o power ? 1.8v memory power supply ? 3.0 v pll power supply ? 3.3 v supplies for usb and internal dac ? multiple power domain within the core for power management 1.6 ambient operating temperature ? CV2201 and cv2202 operate between -40c to +85c ? cv2203 industrial qualified parts operate between - 40c to +85c; cv2203 automotive qualified parts operate between -40c to +125c free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 16/69 2 system design considerations 2.1 cv220x boot-up and configuration when the asic is removed from reset there are a number of activities that must occur before the hardware (and the external memory) is ready for software use. the following must occur: 1. the internal clocks and plls have to be conf igured and locked to the default clock frequencies. 2. the external memory controlle r must be configured appropriately. 3. ddr sdram initialization must occur. all of this activity has associated with it some confi gurable aspects. this configurab ility is communicated to the boot-up hardware through power-up default settings. to configure the boot-up configurable parameters, a subset of the dip dat a bus pins (dip_d) are sampled when reset is de-asserted and pull-up/pull-down resistors are used to set the various configurations. the dip_d pins are tri-stated by default and this allows t he pull-up and pull-down values to be sampled. the following table describes the configurable options. configurable feature dip_d pins (default) operation enables full-on power domain usage by default dip_d[7] (pd) 0 = the ?full on? power domain will not be powered by default. 1 = the ?full on? power domain will be powered by default. enable ecc checking for nand flash booting dip_d[6] (pd) 0 = disabled 1 = enabled boot loader mode. see section 2.3 for a more detailed description on boot load modes of operation. dip_d[5-3] (pd,pu,pd) 000 = this mode used for debug only 001 = code loaded via spi port from a generic serial flash 011 = code loaded via spi port from an atmel dataflash memory 010 = reserved 100 = code loaded from nand flash selects memory controller clocking configuration dip_d[2] (pd) 0 = async mode the memory pll is the clock source for the memory controller. 1 = reserved free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 17/69 configurable feature dip_d pins (default) operation pll configuration. this indicates what configuration (nf,nr,no and range) to apply to the ap and system pll so that the internal clocks are 96mhz. dip_d[1-0] (pu,pd) 00 ? input clk = 13mhz 01 ? input clk = 19.2mhz 10 ? input clk = 24mhz 11 ? input clk = 27mhz table 2-1: cv220x boot-up configurable options the bootup process can be regular or ?secure? for CV2201 and cv2202 parts. the setting of the ?hw_deep_secure? pin controls which booting method is used. only the regular boot process applies to the cv2203 device. ? hw_deep_secure = 0 : regular boot process is used ? hw_deep_secure = 1 : secure boot process is used for the secure boot method, the binary image is run through the crypto block to produce a signature. a comparing signature is appended to the end of the download image and the bootloader checks the generated image against this downloaded value. if a mismatch occurs, the arm remains in reset. also during secure boot, arm jtag access is blocked (no debugger access). access may be reclaimed by software after the arm has been removed from reset (i.e. after the downloaded binary image has been verified as valid). free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 18/69 2.2 boot-up timeline the following timeline illustrates events that occu r during a successful boot sequence. the internal configuration and software binary image must be resident in the spi device or nand flash prior to initiating the boot-up sequence. chip reset de-asserted dip_data pins sampled for configuration core reset de-assserted cfg memory controller initialize dram put controller in ?run? mode copy image to memory remove arm from reset figure 2: boot-up sequence timeline it is possible to skip some steps in the boot-up sequence. for instance, if the software image was previously downloaded and the dram was put into self refresh mode, then the dram initialization and code download steps would not be necessary. the two interfaces that may be used to ?boot? the asic are: ? spi interface ? booted using either the atme l dataflash or industry standard serial flash ? nand flash interface ? booted from industry standar d nand flash. the nand flash must be a large block (2k) and must support a dual read command (read command=0x0 followed by a confirm read command=0x30) 2.3 boot load modes the hardware boot loader block facilitates code loading from different external interfaces. the external interface gets data from an external dev ice and the boot loader block moves the data from the receive fifo to either external memory or cmem. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 19/69 while the boot loader is operating, the arm is held in re set so that it does not st art executing code until the complete program store is in place. when the byte counter expires, indicating all code has been copied, the boot loader indicates to the reset block that the arm can be removed from reset. possible boot loader configurations, as specified by t he downloaded configuration inform ation, are identified in the table below. dip_data[5:3] description 000 this setting will not invoke the boot loader and the arm will be removed from reset immediately. this is a debug mode of operation. code must be written to memory through some other means (ie. jtag port). 011 code is resident in a serial nand flash c onnected to the spi port. the serial flash memory is an atmel dataflash memory that supports the ?continuous array read? command (0xe8). 001 code is resident in a serial nand flash c onnected to the spi port. the serial flash memory is an industry standard memory that supports the ?read data bytes? command (0x03). 010 this setting is reserved and should not be used.; 100 code is resident in nand flash. the nand flash block read sequence is: a. after reset is de-asserted, the bootloader will issue a ?reset? command (?ff?) followed by a 25 usec delay. b. the boot loader then issues the page read command (?00?) and 5 bytes of address (all ?0?). this is followed by a read confirm command (?30?). c. before proceeding further, a 50usec delay occurs. d. a 2kbyte page is then read. if ecc is enabled four 512byte page reads are issued. table 2-2: configuring boot load using dip_data[5:3] pins if booting from nand flash, there is an optional ecc checking mode that may be enabled via a software register. if ecc checking is enabled, the boot_loader checks for errors after a block is read from the device. upon error detection, the boot loader keeps the arm in reset. 2.4 low power configurations some system operating modes require limited cv220x functionality in which case the icp may operate in a low power mode. the cv220x is comprised of multiple volt age islands that enable various low power configuration scenarios. the voltage islands are intended to be activa ted in a cumulative manner based on the particular functionality required. the power confi gurations are listed below. the list is organized with the least functionality and power first, followed by in creasing functionality and power. 1. low power audio/video ? this mode adds to the low power passthrough mode appropriate circuitry for low power mp3 decoding as well as some display functionality. 2. full-on power ? this mode activates the rest of the cv220x functionality. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 20/69 the low power mode is achieved by disconnecting the core power. this mode removes any power drain associated with core leakage. in addition to the modes listed above, the cv220x is des igned in such a way that each block may individually have its clock gated under software control. this provi des a mechanism to lower power consumption for an application that does not require functionality from a ll blocks. also many of the blocks have a hardware controlled mechanism that allows each block to gate its own clock when it is idle and remove the clock gating when activity resumes. this mechanism may be disabled by software if desired. 2.5 reset the internal reset architecture is controlled by an ex ternal reset pin and also by software initiated reset requests. the external reset pin, when asserted, keeps the entire chip in a reset state. after the power supply voltages have stabilized, the external rese t must remain asserted for 1 sec. after the external reset is removed, the timing generation block is removed from reset and starts a timer to time the pll lock interval. the timing generation block keeps the rest of the chip in reset unt il this interval has expired and the clocks are stable. figure 3 illustrates the time line of ev ents that occur within the chip when the external reset is de-asserted. power supply external reset pll locked internal reset 1 usec 0.5 msec figure 3: power-up reset timing waveform figure 4 shows the internal reset architecture. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 21/69 timing generation system registers watchdog boot loader reset block external reset bootloading enabled arm register write delayed reset arm held in reset software block reset watchdog expired block resets figure 4: reset architecture free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 22/69 3 hardware architecture figure 5 shows the cv220x hardware block diagram. uart uart audio i2s/ac?97 i 2 c smart card gpio keypad mmc plus sd/sdhc spi spi mp2ts mp2ts dip sensor h/w cryptographic acceleration usb 2.0 otg 2d graphics osd resize rotate arm926ej-s pll i/f pll dip pll mem pll system pll ap cv220x icp memory controller tv encoder & dac tv out i/f timing generation apex arm926ej-s h.264 ip/lf multi-channel dma image/video processing vld bit pack bit unpack vlc array processing unit nand flash stacked or external nand flash (ext) ddr sdram 128mbit stacked or up to 1gbit external figure 5: cv220x hardware architecture free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 23/69 3.1 peripherals the following subsections provide physical informati on for each of the peripherals. figures show the connectivity between the cv220x image cognition proce ssor and peripherals. tables list the cv220x pin information corresponding to each peripheral interface. 3.1.1 sensor interface the sensor interface receives data from one of two sour ces ? the external sensor or from memory. supported formats of input data from the sensor are: ? yuv422 stream ? encoded jpeg supported formats of input data from memory are: ? yuv422 stream ? yuv420 planar note that the sensor interface block may be progr ammed to accept yuv422 data in uyvy, yuyv, vyuy and yvyu formats. input image sizes up to 12 mpixels are supported at clock frequencies up to 160mhz. output image formats supported by t he sensor interface block are: ? yuv422 stream ? yuv 420 planar ? rgb 565 ? encoded jpeg the sensor interface also prov ides the following functionality: ? scale down: ? average mode scaling by: 1, 1/2, 1/4 and 1/8 ? decimation mode scaling by : horizontal and vertical decimation ? adaptive luminance using histogram table build or gamma correction ? image effects: ? edge enhancement ? image smoothing using a lpf with 9 taps for luminance and 5 taps for chrominance coefficients free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 24/69 ? grey scale ? sepia ? negative ? emboss ? sketch ? woi (window of interest) used for cropping the input image table 3-1 lists the cv220x external pinout of the sensor interface. signal alternate function pin direction pin description sensor_d[9:0] - input sensor data sensor_pclk - input sensor pixel clock sensor_rclk - input sens or horizontal sync signal sensor_fclk - input sensor vertical sync signal sensor_clkout gpio[1] bi-dir. sensor source clock or alternate function sensor_fodd gpio[52] bi-dir. field ( odd, even) or alternate function sensor_gpio gpio[53] bi-dir. sens or gpio or alternate function table 3-1: sensor interface external pinout 3.1.2 keypad scan interface the cv220x has an optional keyscan capability. the key scan processor has four output scan ports and four input scan ports to allow recognition of up to 16 keys. the keyscan interface provides the following features: ? programmable key scan and sense polarity ? programmable scan time ? programmable scan matrix ? auto clearing of the sense value after it has been read ? supports typing mode and gaming mode figure 6 shows the keyscan system implementation. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 25/69 keyscan_out1 internal configurable pull-up keyscan_out2 keyscan_out3 keyscan_in3 keyscan_in2 keyscan_in1 keyscan_in4 keyscan_out4 figure 6: keyscan system implementation table 3-2 lists the cv220x pin information for the key scan interface. to enable the keyscan interface, the alternate function register must be programmed accordingly. signal keyscan function pin direction pin description reserved_14 gpio[45] or keyscan_out3 bi -dir. gpio or alternate function reserved_13 gpio[44] or keyscan_out2 bi -dir. gpio or alternate function reserved_12 gpio[43] or keyscan_out1 bi -dir. gpio or alternate function reserved_11 gpio[42] or keyscan_out0 bi -dir. gpio or alternate function reserved_10 gpio[41] or keyscan_in3 bi -dir. gpio or alternate function reserved_9 gpio[40] or keyscan_in2 bi -dir. gpio or alternate function reserved_8 gpio[39] or keyscan_in1 bi -dir. gpio or alternate function reserved_7 gpio[38] or keyscan_in0 bi -dir. gpio or alternate function table 3-2: keyscan interface free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 26/69 3.1.3 system memory system memory is either integrated on board, or available externally. syst em memory configurations for the devices belonging to the cv220x family of icps are shown in the table below. product memory CV2201 128mbit stacked mobile ddr sdram cv2202 interface to external ddr sdram up to 1gbit in size; compatible with dram with 13 address bits; cv2203 128mbit stacked mobile ddr sdram; table 3-3: cv220x system me mory configufigurations 3.1.4 nand flash interface the CV2201 and cv2202 products have a nand flash interfac e for connectivity to an external nand flash device. the cv2203 device has a 1gbit nand flash sta cked on chip and therefore no external interface connectivity is provided with the exc eption of a write protect pin. the fo llowing list details specific nand flash features: ? 8-bit datapath ? software configurable external control signal timing ? incoming and outgoing datapath implemented using fifos ? software controlled command and page address ? read/write datapath that bypasses t he fifo and allows direct access ? configurable page size ? nand flash read and write algorithms are software driven ? optional hardware ecc support; a simple ecc (1bit correct, 2 bit detect) as well as a reed solomon ecc algorithm (4 bit correct) ? supports up to 4 external chip selects figure 7 shows the connection between the CV2201 or cv 2202 and a typical external nand flash device. it should be noted that the ?ry_by? signal is not a dedicated pin on the CV2201 or cv2202. instead this connection, required for command status, is made to a gpio. alternatively, a software managed polling routing may be used to determine when various commands are completed. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 27/69 nand flash CV2201 or cv2202 nand_d[7:0] nand_cle nand_cen[3:0] nand_ren nand_wen nand flash interface data csn wen oen data[7:0] nand_ale nand_cle nand_ale ry_by gpio figure 7: nand flash connectivity table 3-4 lists pin information fo r CV2201 and cv2202 nand flash interface. signal alternate function pin direction pin description nand_d[7:0] gpio[81:74] or mmcplus_data[7:0] bi-dir. nand data bus or alternate function nand_cle gpio[11] bi-dir. command latch enable or alternate function nand_ale gpio[10] bi-dir. address latch enable or alternate function nand_cen[0] gpio[12] or mmcplus _clk bi-dir. chip select or alternate function nand_cen[1] gpio[70] or mmcplus_cmd bi-dir. chip select or alternate function nand_cen[2] gpio[71] or spi_rxd1 bi-dir. chip select or alternate function nand_cen[3] gpio[72] or spi_rxd2 bi-dir. chip select or alternate function nand_ren gpio[14] bi-dir. read enabl e or alternate function nand_wen gpio[13] bi-dir. write enable or alternate function wp_n - input active low this signal provides hardware protection against unwanted program or erase options for the stacked nand flash device cv2203. table 3-4: nand flash interface 3.1.5 display interface port and tv output the display interface port (dip) interfaces the CV2201 or cv2202 to an external video/display device such as an lcd or a television. note that the cv2203 device does not interface to an lcd, but like the CV2201 and cv2202, this part does include a tv out interface for direct connectivity to a television. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 28/69 the external display controller in the CV2201 and cv2202 devices may be an rgb lcd and four cpu-like interface devices (mipi/non-mipi compliant). the dip has the following features: ? picture-in-picture achieved through dma descriptor fetching of appropriate image data ? color format resizing (rgb24 -> rgb666/rgb565; rgb 666->rgb24/rgb565; rgb565->rgb24/rgb666, yuv422->yuv444) ? display bus interface (dbi): drives an lcd, lcd c ontroller or cpu-type interface. four chip selects are available to support up to four devices includi ng any combination of lcd controllers and/or other devices with cpu-type interfaces. ? timing interface: drives an external video device (r bg lcd) with hsync/vsync/blank signals; when this mode is enabled, no cpu-lcd devices may be used. th is interface supports up to xga resolution. ? tv interface: this analog interface derives ti ming information from an internal ntsc/pal video encoder to drive video data at correct intervals. maximum resolution supported is 640x480 (vga). figure 8 shows a configuration with dual lcds and a tv connection to the dip. in this case, the internal cv220x video encoder and dac are used to derive the analog tv signal. lcd data cs oe we rs tv lcd cv220x dip_d data dip_csn0 cs dip_csn1 dip_oen dip_rs oe we dip_wrn dac_io rs video_in second lcd dip_csn2 dip_csn3 dac_avdd dac_avss dac_vref_in dac_rset dac_vref_out dac_comp 10uf 0.01uf 0.1uf 75 ohm 1.02kohm (+/- 1%) 3.3v figure 8: cpu-type lcd and tv connected to dip (using internal dac) free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 29/69 the figure below illustrates timing for dbi connectivity to a cpu-type interface. figure 9: dbi to cpu-type display waveform diagram table 3-5 lists the CV2201 and cv2202 pin information fo r the dip. the dac signals correspond to the tv output feature available for all cv220x products. CV2201, cv2202 signal alternate function pin direction pin description dip_d[23] gpio[51] or uart1_txd bi-dir. digital video data or alternate function dip_d[22] gpio[50] or uart1_rxd bi-dir. digital video data or alternate function dip_d[21] gpio[49] bi-dir. digital video data or alternate function dip_d[20] gpio[48] bi-dir. digital video data or alternate function dip_d[19] gpio[47] bi-dir. digital video data or alternate function dip_d[18] gpio[46] bi-dir. digital video data or alternate function dip_d[17] gpio[3] or scl_sec bi-dir. digital video data or alternate function dip_d[16] gpio[4] or sda_sec bi-dir. digital video data or alternate function dip_d[15:0] (1) - bi-dir. digital video data bus dip_pclk gpio[5] bi-dir. digital video pixel clock or alternate function free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 30/69 CV2201, cv2202 signal alternate function pin direction pin description dip_oen gpio[15] or dip_blank bi-dir. digital video output enable or alternate function dip_rs dip_hsync output digital video regi ster select or alternate function dip_wrn dip_vsync output digital vi deo write enable or alternate function dip_csn0 - output digital video chip select 0 dip_csn1 - output digital video chip select 1 dip_csn2 gpio[24] bi-dir. digital video ch ip select 2 or alternate function dip_csn3 gpio[25] bi-dir. digital video ch ip select 3 or alternate function dip_cpu_vsync gpio[54] bi-dir. external synchronization frame pulse or alternate function cv220x signal alternate function pin direction pin description dac_comp - analog output analog output of the dac; signal can drive 1.0 vpp on 75 ohm load dac_vref_out - analog output voltage reference output. this output delivers 1.140v reference voltage from cell. it is normally connected to the vrefin pin. dac_rset - analog in/out an external resistor rset connecting dac_rset pin to avss adjusts the magnitude of the dac full- scale output current. recommended setting is 1.02kohm with 1% tolerance. dac_vref_in - analog input reference voltage input. it is suggested to place 0.1uf ceramic capacitor between this pin and avss pin externally. dac_io - analog output analog output pin (with driv e strength) to which a resistor and capacitor is attached to ground to set the output current of the dac (1) the dip_d[7:0] pins of cv2203 are us ed only for sampling at bootup to estab lish the device?s configuration. cv2203 does not include a display interface for connecting to an lcd. table 3-5: display interface 3.1.6 mpeg2 transport interface (mp2ts) the cv220x uses the mp2ts interface to receive mpeg 2 transport streams from t he baseband. this is a four- signal interface and all signals are sourced from the baseband. note that the cv220x device has dual mp2ts interfaces referred to as ?mp2ts? and ?mp2ts1?. the ?m p2ts1? signals are available via shared i/os with the spi interface. refer to table 3-19 for details. the baseband sends out 188-byte frames and a typical fram e has the following signal format. the interface can be configured to support msb or lsb first formats. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 31/69 figure 10: mp2ts interface signal formats table 3-6 lists the cv220x pin info rmation for the mp2ts interface. signal alternate function pin direction pin description mp2ts_clk - input clock source for synchronous interface mp2ts_valid - input signal indicating the serial data is valid mp2ts_sync - input frame pulse indicating start of frame mp2ts_data - input serial data table 3-6: mp2ts interface 3.1.7 usb 2.0 high speed the usb interface has the following features: ? usb 2.0 high speed compliant ? CV2201 and cv2202 devices support usb otg ? usb 2.0 phy is integrated on chip ? supports high-speed (480 mhz), full speed ( 12 mhz), and low speed (1.5 mhz) operation ? supports seven physical endpoints - one control and six endpoints configurable as in or out. the in/out endpoints are software configurable as bulk, isochronous, interrupt or control table 3-7 lists the cv220x pin information for the usb interface. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 32/69 signal alternate function pin direction pin description usb_phy_id - analog usb pad indicates a or b cable usb_phy_vbus - analog usb pad vbus power monitor input. this is a 5 v signal (+/-10%) with a max value of 5.5v. usb_phy_plus - analog usb pad usb data plus usb_phy_minus - analog usb pad usb data minus usb_phy_res - analog usb pad external resistor of 8.2 k 1% should be connected from here to ground utmiotg_drvvbus gpio[73] bi-dir. externally controls power source for usb vbus voltage or alternate function; available for CV2201 and cv2202 devices; table 3-7: usb interface the usb_phy_vbus signal monitors the 5. 0v vbus signals for usb 2.0 high speed. figure 11 illustrates usb interface connectivity with the host. figure 11: usb/host connectivity free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 33/69 3.1.8 smart card interface the smart card interface complies with the following integrated circuit card standards: ? iso/iec 7816-3 amendment i (2002-06-01) ? iso/iec 7816-10 ? emv book 1 version 4.1 (2004-05-01) the cv220x smart card feature supports: ? programmable clock frequency, baud rate, acti vation time, de-activation time and others ? hardware initiated de-activation sequence upon detection of card removal ? charge pump control interface for smart card power supply control figure 12 shows the connection between the cv 220x and a typical smart card device. figure 12: smart card connectivity table 3-8 lists the cv220x pin informat ion for the smart card interface. signal alternate function pin direction pin description sc_io gpio[58] bi-dir. serial data i/o sc_card_detect gpio[59] bi-dir. card detection sc_card_voltage gpio[61] or spi_rx3 bi-dir. output to external ps to indicate required voltage or alternate function free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 34/69 signal alternate function pin direction pin description sc_fcb gpio[57] or pwm1_out bi-dir. used in synchronous mode or alternate function sc_clk gpio[55] bi-dir. clock or alternate function sc_power_on gpio[60] bi-dir. controls external ps or alternate function sc_rst gpio[56] bi-dir. reset or alternate function table 3-8: smart card interface 3.1.9 serial interfaces the cv220x has the following serial interfaces: ? uart ? spi 3.1.9.1 uart the cv220x has two uarts, referred to as uart and uart1, used for incoming or outgoing data paths. note that uart1_rx and uart1_tx signals of uart1 are ava ilable via shared i/os and this uart does not support cts/rts modem signals. the uarts have the following features: ? asynchronous interface ? programmable baud rate ? parity and framing error detection with indication via interrupts ? echo, local loopback and remote loopback diagnostic modes ? single start bit, 8-bit character length, programmabl e stop bits (1 or 2), programmable parity (even, odd or none) ? independent receive and transmit fifos ? the primary uart supports cts/rts m odem signals for hardware flow control. table 3-9 lists the cv220x pin info rmation for the uart interface. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 35/69 signal alternate function pin direction pin description uart_rx gpio[23] bi-dir. uart serial receive data or alternate function uart_tx gpio[22] bi-dir. uart serial transmit data or alternate function uart_cts gpio[82] or spi_cs1 bi-dir. clear to send modem signal or alternate function uart_rts gpio[83] or spi_cs2 bi-dir. request to send modem signal or alternate function table 3-9: uart interface uart1 signals are accessible only as alter nate functions. these signals are listed in table 3-19: gpios and alternate functions shared with external pins. 3.1.9.2 spi the serial peripheral interface (spi) provides an alternate data path to and from the cv220x. the cv220x device has two spi blocks on board referred to herei n as spi and spi1. the spi blocks in the CV2201 and cv2202 devices each have four chip selects (spi_cs, spi_ cs1, spi_cs2, spi_cs3), four serial receive data signals (spi_rx, spi_rx1, spi_rx2, sp i_rx3) and a serial transmit data signal (spi_tx). (note that three of the chip selects and three receive signals of spi are a ccessible via shared i/os). cv2203-a spi has two chip selects (spi_cs, spi_cs3), two serial receive data signals (spi_rx and spi_rx3) and a serial transmit data signal (spi_tx). (the spi_cs3 and spi_rx3 are accessible as alternate functions for this device.) for more details, refer to table 3-19.) spi1 has a dedicated clock, a chip select, and transmit and receive i/os as shown below in table 3-10. this interface is compatible with the motorola spi specification and provi des the following features: ? four wire synchronous full duplex interface using a clock, chip select, serialized receive data and serialized transmit data ? configurable as master or slave. the master s ources the clock and chip select and the slave sinks these pins. ? 128-byte transmit fifo and 128-byte receive fifo ? programmable clock rate (master mode only) ? programmable frame size ? supports ?continuous? mode of operation ? programmable clock phase (sph) and polarity (spo) table 3-10 lists the cv220x pin information for the spi. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 36/69 signal alternate function pin type pin description spi_clk gpio[29] bi-dir. spi seri al clock or alternate function spi_cs gpio[28] bi-dir. spi slav e select or alternate function spi_tx gpio[26] bi-dir. spi serial transmit data or alternate function spi_rx gpio[27] bi-dir. spi serial receive data or alternate function spi1_clk mp2ts1_clk bi-dir. spi1 se rial clock or alternate function spi1_cs mp2ts1_sync bi-dir. spi1 sl ave select or alternate function spi1_tx mp2ts1_valid bi-dir. spi1 serial transmit data or alternate function spi1_rx mp2ts1_data bi-dir. spi1 serial receive data or alternate function table 3-10: spi signals 3.1.10 gps inteface the spi block has an embedded alternate gps function that stores data from a gps source into the receive fifo. when this mode is enabled the spi function can no l onger use the receive fifo (the transmit fifo is still available for spi transmit functions). the gps interface is a very simple serial interface as shown below. gps_clk gps_s gps_m0 gps_m1 (optional) gps_m2 (optional) figure 13: gps interface gps interface signals are shared ios of the mp2ts inte face and the uart interface. gps interface signals are listed in the table below. signal alternate function pin direction pin description mp2ts_clk gps_clk bi-dir. mp2ts clock or alternate function mp2ts_valid gps_m0 bi-dir. mp2ts valid serial data or alternate function free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 37/69 signal alternate function pin direction pin description mp2ts_sync gps_m1 bi-dir. mp2ts frame pulse or alternate function mp2ts_data gps_s bi-dir. mp2ts serial data or alternate function uart_rts gps_m2 bi-dir. request to send modem signal or alternate function table 3-11: gps interface 3.1.11 audio interface the audio interface provides a direct connection to either voice quality or high-quality audio adc/dac. the audio interface has the following features: ? supports i2s or ac97 interface protocol ? supports full duplex data path ? separate receive and transmit fifos ? software configurable hardware interface to support a variety of i2s and ac97 applications figure 14 shows the CV2201/cv2202 audio interface c onnections to an audio dac. the cv2203 device does not include an audio interface. audio dac CV2201/ cv2202 audio_clkr audio_clkx audio_dr audio interface clkr dr clkx dx audio_dx audio_fsr audio_fsx fsr fsx mclk clk figure 14: audio interface table 3-12 lists the CV2201 and cv2202 pin in formation for the audio interface. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 38/69 signal alternate function pin direction pin description audio_clkr gpio[16] bi-dir. audio receiv e bit clock or alternate function audio_clkx gpio[19] bi-dir. audio transmi t bit clock or alternate function audio_dr gpio[17] bi-dir. audio rece ive data or alternate function audio_dx gpio[20] bi-dir. audio trans mit data or alternate function audio_fsr gpio[18] or pwm2_out bi-dir. audio receive frame clock or alternate function audio_fsx gpio[21] bi-dir. audio transmi t frame clock or alternate function mclk - bi-dir. audio clock source from external audio dac. table 3-12: audio interface 3.1.12 media storage (sd/sdhc) the media storage interface is compatible with the sd and sdhc memory card specifications. sdhc cards are supported but only at sd card interface rates. mmc is a subset of the sd s pecification and by default is also supported. the media storage in terface has the following features: ? software programmable external clock ? support of a 48-bit command through a software accessible command buffer ? support of both a 48 or 136-bit response through a response buffer ? support of crc generation and checking ? software configurable data width of 1 (mmc mode) or 4 bits (sd mode) ? incoming and outgoing datapath (implemented using fifos) driven by a dma engine the interface does not manage the media card power supply. figure 15 shows the connectivity between the cv220x and an sd memory card. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 39/69 figure 15: media storage interface to sd card table 3-13 lists the cv220x pin informat ion for the media storage interface. signal alternate function pin type pin description sd_clk gpio[35] bi-dir. sd/sdhc clock or alternate function sd_cmd gpio[34] bi-dir. sd/sdhc serial command/response or alternate function sd_d[3:0] gpio[33:30] bi-dir. sd/sdhc serial data or alternate function table 3-13: media storage interface 3.1.13 i 2 c interface the i 2 c controller is a peripheral interface intended for conf iguring external devices such as sensors and audio dacs. the interface consists of the following signals: ? serial clock ? this is a clock to sample an incoming serial data stream or to indicate when an outgoing serial stream has valid data. this serial clo ck pin will ?float? high and ?drive? low much like an open collector and requires an external pull-up resistor. ? serial data ? this is a bi-directional io that c an be driven by either the cv 220x or the peripheral being configured. the serial data pin will ?float? high and ?drive? low much like an open collector and requires an external pull-up resistor. the cv220x has two i 2 c interfaces on chip. one of these interf aces has its serial clock and serial data accessible as alternate functions via shared i/os. the other i 2 c interface has primary functionality on dedicated i/os as shown in the table below. signal alternate function pin direction pin description scl gpio[36] bi-dir. serial configuration clock or alternate function sda gpio[37] bi-dir. serial configurati on data or alternate function table 3-14: i2c interface 3.1.14 mmcplus interface the mmcplus interface is similar to sd interface with the exception that it has a data width of 8-bits. these interface pins in the CV2201 and cv2202 devices are s hared i/os with the nand interface. the mmcplus interface is not available with the cv2203 device. t he table below depicts the si gnals of this interface. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 40/69 signal alternate function pin direction pin description nand_cen[0] gpio[12] or mmcplus_clk bi-dir. nand chip select0 or alternate function nand_cen[1] gpio[70] or mmcplus_cmd bi-dir. nand chip select1 or alternate function nand_d[0] gpio[74] or mmcplus_data[0] bi-dir. nand data bus signal or alternate function nand_d[1] gpio[75] or mmcplus_data[1] bi-dir. nand data bus signal or alternate function nand_d[2] gpio[76] or mmcplus_data[2] bi-dir. nand data bus signal or alternate function nand_d[3] gpio[77] or mmcplus_data[3] bi-dir. nand data bus signal or alternate function nand_d[4] gpio[78] or mmcplus_data[4] bi-dir. nand data bus signal or alternate function nand_d[5] gpio[79] or mmcplus_data[5] bi-dir. nand data bus signal or alternate function nand_d[6] gpio[80] or mmcplus_data[6] bi-dir. nand data bus signal or alternate function nand_d[7] gpio[81] or mmcplus_data[7] bi-dir. nand data bus signal or alternate function table 3-15: mmcplus interface pinout for CV2201, cv2202 3.1.15 external memory interface the cv2202 device has a memory controller capable of in terfacing with an external mobile ddr sdram up to 1gbit in size. figure 16 illustrates the cv2202 connectivity to an external mobile ddr sdram. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 41/69 mobile ddr sdram cv2202 dq[31:0] a[12:0] wen rasn casn cke csn dm[3:0] ba[1:0] dmclk dmclkn clk_n clk clk_ena cs_n we_n cas_n ras_n addr[12:0] bank_addr[1:0] data_mask[3:0] data_q[31:0] data_strobe[3:0] dqs[3:0] figure 16: cv2202 interface to external memory the table below provides cv2202 pin info rmation for the memory interface. signal alternate function pin direction pin description dmclk - output clock signal to external memory. dmclkn - output dmclk and dmclkn are differential clocks to the external memory. a[12:0] - output address bus cke - output clock enable signal for external memory wen - output write enable signal for external memory (active low) casn - output column access strobe (active low) rasn - output row access strobe (active low) csn - output chip select (active low) ba[1:0] - output bank address bus dq[31:0] - bi-dir. data bus free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 42/69 signal alternate function pin direction pin description dm[3:0] - output data mask for write data; dm[3] is mask bit for dq[31:24] dm[2] is mask bit for dq[23:16] dm[1] is mask bit for dq[15:8] dm[0] is mask bit for dq[7:0]; dqs[3:0] - bi-dir. data strobe; dqs[3] is strobe bit for dq[31:24] dqs[2] is strobe bit for dq[23:16] dqs[1] is strobe bit for dq[15:8] dqs[1] is strobe bit for dq[7:0]; table 3-16: cv2202 external memory pinout 3.1.16 pulse width modulated outputs two pulse width modulated (pwm) out puts are available as alternat e pin functions. as shown in table 3-17, these pins also have alternate gpio functionality. to use the pwm functionality, the gpio for the pin must be disabled and the pwm output must be enabled. signal alternate function pin direction pin description audio_fsr gpio[18] or pwm2 bi-dir. audio receive frame clock, gpio or pwm signal as alternate function; only applies to CV2201 and cv2202 sc_fcb gpio[57] or pwm1 bi-dir. smart card, gpio or pwm signal as alternate function; applies to all cv220x parts table 3-17: pwm function pinout 3.1.17 power management interface the pmi controller is a peripheral interface intended to manage internal and external power sources (either to change the voltage level or disable the voltage completely). note that dual master operation is not supported by this controller. the pmi interface is a two wire interf ace consisting of the following signals: ? pmi_clk ? the clock source of this controller. this is only driven during the active portion of a transaction, otherwise it is tri-stated. ? pmi_data ? bi-directional serial data. data is always driven on the rising edge and sampled on the falling edge. free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 43/69 signal alternate function pin direction pin description reserved_4 gpio[7] or pmi_data bi-dir. gpio or alternate function reserved_3 gpio[6] or pmi_clk bi-dir. gpio or alternate function table 3-18: pmi function pinout 3.1.18 gpios and alternate functions a number of external pins have alter nate gpio functionality as shown in table 3-19. some of these pins also have a third function shown in the alternate function colu mn. the ?gpio enable? register controls whether the pin functions as a gpio. for the pins that have a third func tion, the ?alternate function enable? register selects the alternate function if the gpio enable bit for that pin is disabled. note that external pins labeled ?reserved_#? should only be used as gpios or as the alternate func tion as the primary functionality is reserved and not intended for use during normal operation. the last colu mn in the table identifies part numbers which have access to associated gpios and alternate functions. external pin gpio # alternate function pad resistor device access reserved_1 gpio[0] - none cv220x sensor_clkout gpi o[1] - none cv220x reserved_2 gpio[2] - pull-down cv220x dip_d[17]/ reserved_23 gpio[3] scl_sec none CV2201, cv2202/ cv2203 dip_d[16]/ reserved_24 gpio[4] sda_sec none CV2201, cv2202/ cv2203 dip_pclk gpio[5] - none CV2201, cv2202 reserved_3 gpio[6] pmi_clk none cv220x reserved_4 gpio[7] pmi_data none cv220x reserved_5 gpio[8] - none cv220x reserved_6 gpio[9] - none cv220x nand_ale/ reserved_25 gpio[10] - none CV2201, cv2202/ cv2203 nand_cle gpio[11] - none CV2201, cv2202 nand_cen[0]/ reserved_19 gpio[12] mmcplus_clk pull-up CV2201, cv2202/ cv2203 (only gpio) nand_wen gpio[13] - none CV2201, cv2202 nand_ren gpio[14] - none CV2201, cv2202 dip_oen gpio[15] di p_blank none CV2201, cv2202 audio_clkr gpio[16] - none CV2201, cv2202 audio_dr gpio[17] - none CV2201, cv2202 audio_fsr gpio[18] pw m2_out none CV2201, cv2202 audio_clkx gpio[19] - none CV2201, cv2202 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 44/69 external pin gpio # alternate function pad resistor device access audio_dx gpio[20] - none CV2201, cv2202 audio_fsx gpio[21] - none CV2201, cv2202 uart_tx gpio[22] - none cv220x uart_rx gpio[23] - none cv220x dip_csn2 gpio[24] - pull-up CV2201, cv2202 dip_csn3 gpio[25] - pull-up CV2201, cv2202 spi_tx gpio[26] mp2t s1_valid none cv220x spi_rx gpio[27] mp2ts1_d none cv220x spi_cs gpio[28] mp2t s1_sync pull-up cv220x spi_clk gpio[29] m p2ts1_clk none cv220x sd_d[0:3] gpio[30:33] - none cv220x sd_cmd gpio[34] - none cv220x sd_clk gpio[35] - pull-up cv220x scl gpio[36] - none cv220x sda gpio[37] - none cv220x reserved_7 gpio[38] key scan_in[0] none cv220x reserved_8 gpio[39] key scan_in[1] none cv220x reserved_9 gpio[40] key scan_in[2] none cv220x reserved_10 gpio[41] key scan_in[3] none cv220x reserved_11 gpio[42] keyscan_out[0] none cv220x reserved_12 gpio[43] keyscan_out[1] none cv220x reserved_13 gpio[44] keyscan_out[2] none cv220x reserved_14 gpio[45] keyscan_out[3] none cv220x dip_d[18:21]/ reserved_[26:29] gpio[46:49] - none CV2201, cv2202/ cv2203 dip_d[22]/ reserved_17 gpio[50] uart1_rx none CV2201, cv2202/ cv2203 dip_d[23]/ reserved_18 gpio[51] uart1_tx none CV2201, cv2202/ cv2203 sensor_fodd gpio[52] - none cv220x sensor_gpio gpio[53] - none cv220x dip_cpu_vsync gpio[54] - none CV2201, cv2202 sc_clk gpio[55] - pull-up cv220x sc_rst gpio[56] - none cv220x sc_fcb gpio[57] pwm1_out none cv220x sc_io gpio[58] - none cv220x sc_card_detect gpio[59] - none cv220x sc_power_on gpio[60] - none cv220x sc_card_voltage gpio[61] spi_rx3 none cv220x free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 45/69 external pin gpio # alternate function pad resistor device access nand_cen[1]/ reserved_20 gpio[70] mmcplus_cmd pull-up CV2201, cv2202/ cv2203 (only gpio) nand_cen[2]/ reserved_21 gpio[71] spi_rx1 pull-up CV2201, cv2202/ cv2203 nand_cen[3]/ reserved_22 gpio[72] spi_rx2 pull-up CV2201, cv2202/ cv2203 utmiotg_drvvbus gpio[73] - pull-up CV2201, cv2202 nand_d[0:7] gpio[74:81] mmcplus _data[0:7] none CV2201, cv2202 uart_cts gpio[82] spi_cs1 none cv220x uart_rts gpio[83] spi_cs 2 or gps_m2 none cv220x reserved_15 gpio[84] spi_cs3 none cv220x dip_csn0 gpio[86] - pull-up CV2201, cv2202 dip_csn1 gpio[87] - pull-up CV2201, cv2202 mp2ts_d gpio[88] gps_s none cv220x mp2ts_clk gpio[89] gps_clk none cv220x mp2ts_valid gpio[90] gps_m0 none cv220x mp2ts_sync gpio[91] gps_m1 none cv220x dip_rs - dip_hsync none CV2201, cv2202 dip_wrn - dip_vsync none CV2201, cv2202 spi1_clk - mp2ts1_clk none cv220x spi1_cs - mp2ts1_sync pull-up cv220x spi1_tx - mp2ts1_valid none cv220x spi1_rx - mp2ts1_data none cv220x table 3-19: gpios and alternate functions shared with external pins 3.1.19 production test and system signals table 3-20 lists the cv220x pin inform ation for system and test signals. signal alternate function pin direction pin description clkin - input clock input to cv220x from crystal, oscillator or baseband processor clkout - output output for crystal connection or ground if clkin is driven by oscillator resetn - input chip reset hw_deep_secure - input selects secure boot process if set to ?1? or regular boot if set to ?0?; only applicable to CV2201 and cv2202 parts; cv2203 boot is free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 46/69 signal alternate function pin direction pin description always regular. testmode - input enable test mode (manufacture test only) tck - input jtag test clock rtck - output jtag return clock tdi - input jtag test data input tdo - output jtag test data output ntrst - input jtag test reset tms - input jtag test mode table 3-20: production test and system signals 3.1.20 core and i/o power table 3-21 provides the cv220x pin information for core and i/o power. power supply pin names pin description vdd_core power supply for ic core 1.0 v vdd_lp power supply for low power audio/video circuitry 3.0v vdda_pll analog supply voltage for pll * vssa_pll pll power return (do not connect to ground) 1.8 v vdd_sdram sdram core power 2.8 v vdd_osc power supply for crystal pad vdd_usb power supply for usb 3.3 v vdda_dac analog supply voltage for internal dac vdd_sccard io supply for smart card interface (CV2201, cv2202) vdd_sensor io supply for sensor interface block and i2c vdd_gpio io supply for gpios and keyscan (CV2201, cv2202) vdd_dip io supply for dip block (CV2201, cv2202) vdd_miscif io supply for mp2ts, uart, spi, and jtag interfaces. vdd_sdmmc io supply for sd/sdhc/mmc interface (CV2201, cv2202) vdd_audio io supply for audio interface block (CV2201, cv2202) vdd_nand io supply for nand interface block 1.8/2.8/3.0 v vdd_io cv2203 general io supply for mp2ts, jtag, spi, uart, sdmmc, sccard, gpio/keyscan interfaces vss common ground vssa_dac ground for internal analog dac vss_usb ground for usb gnd vss_osc ground for crystal pad * see figure 17 for vssa_pll connectivity free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 47/69 table 3-21: cv220x power supply 3.2 pll and timing generation the timing generation block provides and manages the clocks required by the internal logic and ip blocks. the clocks are produced from an internal pll. an onboard crysta l oscillator or an external clock provides the input clock to the pll. figure 17 shows the connection between crystals and the cv220x. if the clock source is the baseband processor or an oscillator, the clock output signals are not connected. figure 17: crystal connected to cv220x free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 48/69 4 packaging 4.1 CV2201 the CV2201 is available in a 236-ball bga package of size 9 mm x 9 mm x 1.34 mm. figure 18 contains cv220x packaging information. all dimensions are in mm. figure 18: CV2201 package free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 49/69 4.2 cv2202 the cv2202 is available in a 296-ball cabga package of size 10 mm x 10 mm x 0.99 mm. figure 19 contains cv220x packaging information. all dimensions are in mm. figure 19: cv2202 package free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 50/69 4.3 cv2203 the cv2203 is available in a 196-ball bga package of size 10 mm x 10 mm x 1.44 mm. figure 20 contains cv220x packaging information. all dimensions are in mm. figure 20: cv2203 package free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 51/69 4.4 cv220x pinout the following table describes the physical pins of t he devices belonging to the cv220x series. the pins are organized into functional groups. exte rnal interfaces are grouped together on the io voltage banks that can be powered by either 2.8 or 1.8 volts. many outputs may be configured as hav ing low or high output drive strength by programming the device. the output drive c apability is indicated in the pad type column. note that ?-? indicates the pin does not apply to the devic e as the signal is not balled out on the package. pins in the ?no connect? section of the table are used sole ly for test purposes and should not be used in normal operating mode. some pins are designated ?reserved_#? . these pins may only be used as the corresponding gpios or alternate functionality as defined in section 3.1.18. primary functionality of these pins is reserved and not intended for use. pin name power domain pad type default pu/pd CV2201 ball cv2202 ball cv2203 ball sensor sensor_d[0] sif input pd c6 e6 a4 sensor_d[1] sif input pd c7 d7 c5 sensor_d[2] sif input pd d7 e7 b5 sensor_d[3] sif input pd e7 c8 a5 sensor_d[4] sif input pd b8 d8 c6 sensor_d[5] sif input pd c8 e8 b6 sensor_d[6] sif input pd d8 c9 a6 sensor_d[7] sif input pd e8 d9 c7 sensor_d[8] sif input pd b9 e9 b7 sensor_d[9] sif input pd c9 d10 a7 sensor_fclk sif input pd b11 e11 c8 sensor_pclk sif input pd e9 d11 b8 sensor_rclk sif input pd d9 e10 a8 sensor_fodd sif bi-dir. 4 ma / 8 ma none c10 e12 b9 sensor_gpio sif bi-dir. 4 ma / 8 ma none b7 d6 b4 sensor_clkout sif bi-dir. 4 ma / 8 ma none b10 d12 a9 i2c scl sif bi-dir. 4 ma / 8 ma none e10 d14 b10 sda sif bi-dir. 4 ma / 8 ma none d10 d13 c9 nand nand_wen nand bi-dir. 2 ma / 4 ma none r1 v1 - nand_ren nand bi-dir. 2 ma / 4 ma none t1 v2 - nand_cen[3] nand bi-dir. 2 ma / 4 ma pu k3 u3 - nand_cen[2] nand bi-dir. 2 ma / 4 ma pu t2 t3 - nand_cen[1] nand bi-dir. 2 ma / 4 ma pu r2 r3 - nand_cen[0] nand bi-dir. 2 ma / 4 ma pu p2 p3 - nand_ale nand bi-dir. 2 ma / 4 ma none l3 v3 - free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 52/69 pin name power domain pad type default pu/pd CV2201 ball cv2202 ball cv2203 ball nand_cle nand bi-dir. 2 ma / 4 ma none m3 p4 - nand_d[0] nand bi-dir. 2 ma / 4 ma none n3 r4 - nand_d[1] nand bi-dir. 2 ma / 4 ma none p3 t4 - nand_d[2] nand bi-dir. 2 ma / 4 ma none k4 u4 - nand_d[3] nand bi-dir. 2 ma / 4 ma none n4 v4 - nand_d[4] nand bi-dir. 2 ma / 4 ma none p4 r5 - nand_d[5] nand bi-dir. 2 ma / 4 ma none k5 t5 - nand_d[6] nand bi-dir. 2 ma / 4 ma none n5 u5 - nand_d[7] nand bi-dir. 2 ma / 4 ma none n6 v5 - wp_n nand input none - - k5 dac dac_comp dac analog i/o none l2 t1 n2 dac_vref_out dac analog i/o none m1 t2 p2 dac_rset dac analog i/o none m2 u2 n3 dac_vref_in dac analog i/o none n2 u1 p3 dac_io dac analog i/o none l1 r1 n1 display interface port dip_d[0] dip bi-dir. 4 ma / 8 ma pd k16 l16 m8 (1) dip_d[1] dip bi-dir. 4 ma / 8 ma pu k15 l15 n8 (1) dip_d[2] dip bi-dir. 4 ma / 8 ma pd k14 l14 p8 (1) dip_d[3] dip bi-dir. 4 ma / 8 ma pd k13 m16 m9 (1) dip_d[4] dip bi-dir. 4 ma / 8 ma pu j13 m15 n9 (1) dip_d[5] dip bi-dir. 4 ma / 8 ma pd l16 m14 p9 (1) dip_d[6] dip bi-dir. 4 ma / 8 ma pd l15 n18 l10 (1) dip_d[7] dip bi-dir. 4 ma / 8 ma pd l14 n17 m10 (1) dip_d[8] dip bi-dir. 4 ma / 8 ma pd l13 n16 - dip_d[9] dip bi-dir. 4 ma / 8 ma none m16 n15 - dip_d10] dip bi-dir. 4 ma / 8 ma none m15 n14 - dip_d[11] dip bi-dir. 4 ma / 8 ma none m14 p18 - dip_d[12] dip bi-dir. 4 ma / 8 ma none m13 p17 - dip_d[13] dip bi-dir. 4 ma / 8 ma none n16 p16 - dip_d[14] dip bi-dir. 4 ma / 8 ma none n15 p15 - dip_d[15] dip bi-dir. 4 ma / 8 ma none n14 r18 - dip_d[16] dip bi-dir. 4 ma / 8 ma none n13 r17 - dip_d[17] dip bi-dir. 4 ma / 8 ma none p16 r16 - dip_d[18] dip bi-dir. 4 ma / 8 ma none p15 t18 - dip_d[19] dip bi-dir. 4 ma / 8 ma none r16 t17 - dip_d[20] dip bi-dir. 4 ma / 8 ma none r15 u18 - dip_d[21] dip bi-dir. 4 ma / 8 ma none t16 u17 - free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 53/69 pin name power domain pad type default pu/pd CV2201 ball cv2202 ball cv2203 ball dip_d[22] dip bi-dir. 4 ma / 8 ma none t15 v18 - dip_d[23] dip bi-dir. 4 ma / 8 ma none t14 v17 - dip_rs dip output 4 ma / 8 ma none r14 u16 - dip_csn0 dip output 4 ma / 8 ma pu r13 v16 - dip_csn1 dip output 4 ma / 8 ma pu t13 v15 - dip_csn2 dip bi-dir. 4 ma / 8 ma pu r12 u15 - dip_csn3 dip bi-dir. 4 ma / 8 ma pu p12 r15 - dip_wrn dip output 4 ma / 8 ma none n12 r14 - dip_oen dip bi-dir. 4 ma / 8 ma none r11 p14 - dip_pclk dip bi-dir. 4 ma / 8 ma none n11 p13 - dip_cpu_vsync dip bi-dir. 4 ma / 8 ma none p11 r13 - uart uart_rx miscif bi-dir. 2 ma / 4 ma none a2 e2 c4 uart_tx miscif bi-dir. 2 ma / 4 ma none b1 e3 c3 uart_cts miscif bi-dir. 2 ma / 4 ma none b2 d4 c2 uart_rts miscif bi-dir. 2 ma / 4 ma none c1 e4 c1 spi spi_clk miscif bi-dir. 2 ma / 4 ma none c2 f1 d4 spi_cs miscif bi-dir. 2 ma / 4 ma pu c3 f2 d3 spi_tx miscif bi-dir. 2 ma / 4 ma none c4 f3 d2 spi_rx miscif bi-dir. 2 ma / 4 ma none c5 f4 d1 spi1_clk miscif bi-dir. 2 ma / 4 ma none d1 g1 e4 spi1_cs miscif bi-dir. 2 ma / 4 ma pu d2 g2 e3 spi1_tx miscif bi-dir. 2 ma / 4 ma none d3 g3 e2 spi1_rx miscif bi-dir. 2 ma / 4 ma none d4 g4 e1 media storage sd_clk sdmmc bi-dir. 4 ma / 8 ma none f1 j1 g4 sd_cmd sdmmc bi-dir. 4 ma / 8 ma none f2 j2 g3 sd_d[0] sdmmc bi-dir. 4 ma / 8 ma none f3 j3 g2 sd_d[1] sdmmc bi-dir. 4 ma / 8 ma none g1 j4 g1 sd_d[2] sdmmc bi-dir. 4 ma / 8 ma none g2 h5 h1 sd_d[3] sdmmc bi-dir. 4 ma / 8 ma none g3 j5 h2 audio audio_clkr audio bi-dir. 2 ma / 4 ma none p10 p12 - audio_clkx audio bi-dir. 2 ma / 4 ma none n10 r11 - audio_dr audio bi-dir. 2 ma / 4 ma none m10 p11 - audio_dx audio bi-dir. 2 ma / 4 ma none n9 r10 - audio_fsr audio bi-dir. 2 ma / 4 ma none m9 p10 - audio_fsx audio bi-dir. 2 ma / 4 ma none n8 r9 - free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 54/69 pin name power domain pad type default pu/pd CV2201 ball cv2202 ball cv2203 ball mclk audio bi-dir. 2 ma / 4 ma none m8 p9 - mp2ts mp2ts_clk miscif input n.a. e1 h1 f4 mp2ts_valid miscif input n.a. e2 h2 f3 mp2ts_sync miscif input n.a. e3 h3 f2 mp2ts_data miscif input n.a. e4 h4 f1 usb usb_phy_id usb usb pad n.a. j5 n3 l4 usb_phy_vbus usb usb pad n.a. j4 n2 l3 usb_phy_plus usb usb pad n.a. k1 n1 l1 usb_phy_minus usb usb pad n.a. j1 m1 k1 usb_phy_res usb usb pad n.a. j3 m2 k3 utmiotg_drvvbus audio bi-dir. 4 ma / 8 ma pu r10 r12 - smart card sc_io sccard bi-dir. 4 ma / 8 ma none h1 k1 h3 sc_card_detect sccard bi-dir. 4 ma / 8 ma none h2 k2 h4 sc_card_voltage sccard bi-dir. 4 ma / 8 ma none h3 k3 j1 sc_fcb sccard bi-dir. 4 ma / 8 ma none h4 k4 j2 sc_clk sccard bi-dir. 4 ma / 8 ma pu h5 l1 j3 sc_power_on sccard bi-dir. 4 ma / 8 ma none h6 l2 j4 sc_rst sccard bi-dir. 4 ma / 8 ma none j6 l3 k4 sdram dmclk sdram output 4 ma / 8 ma none - v6 - dmclkn sdram output 4 ma / 8 ma none - v7 - a[0] sdram output 4 ma / 8 ma none - t11 - a[1] sdram output 4 ma / 8 ma none - v12 - a[2] sdram output 4 ma / 8 ma none - u12 - a[3] sdram output 4 ma / 8 ma none - t12 - a[4] sdram output. 4 ma / 8 ma none - u6 - a[5] sdram output 4 ma / 8 ma none - t6 - a[6] sdram output 4 ma / 8 ma none - u7 - a[7] sdram output 4 ma / 8 ma none - t7 - a[8] sdram output 4 ma / 8 ma none - v8 - a[9] sdram output 4 ma / 8 ma none - u8 - a[10] sdram output 4 ma / 8 ma none - u11 - a[11] sdram output 4 ma / 8 ma none - t8 - a[12] sdram output 4 ma / 8 ma none - v13 - cke sdram output. 4 ma / 8 ma none - v9 - wen sdram output 4 ma / 8 ma none - u9 - free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 55/69 pin name power domain pad type default pu/pd CV2201 ball cv2202 ball cv2203 ball casn sdram output 4 ma / 8 ma none - t9 - rasn sdram output 4 ma / 8 ma none - v10 - csn sdram output 4 ma / 8 ma none - u10 - ba[0] sdram output 4 ma / 8 ma none - t10 - ba[1] sdram output 4 ma / 8 ma none - v11 - dm[0] sdram output 4 ma / 8 ma none - c14 - dm[1] sdram output 4 ma / 8 ma none - c13 - dm[2] sdram output 4 ma / 8 ma none - a6 - dm[3] sdram output 4 ma / 8 ma none - a5 - dqs[0] sdram bi-dir. 4 ma / 8 ma none - a13 - dqs[1] sdram bi-dir. 4 ma / 8 ma none - b13 - dqs[2] sdram bi-dir. 4 ma / 8 ma none - b6 - dqs[3] sdram bi-dir. 4 ma / 8 ma none - c6 - dq[0] sdram bi-dir. 4 ma / 8 ma none - a16 - dq[1] sdram bi-dir. 4 ma / 8 ma none - b16 - dq[2] sdram bi-dir. 4 ma / 8 ma none - c16 - dq[3] sdram bi-dir. 4 ma / 8 ma none - a15 - dq[4] sdram bi-dir. 4 ma / 8 ma none - b15 - dq[5] sdram bi-dir. 4 ma / 8 ma none - c15 - dq[6] sdram bi-dir. 4 ma / 8 ma none - a14 - dq[7] sdram bi-dir. 4 ma / 8 ma none - b14 - dq[8] sdram bi-dir. 4 ma / 8 ma none - a12 - dq[9] sdram bi-dir. 4 ma / 8 ma none - b12 - dq[10] sdram bi-dir. 4 ma / 8 ma none - c12 - dq[11] sdram bi-dir. 4 ma / 8 ma none - a11 - dq[12] sdram bi-dir. 4 ma / 8 ma none - b11 - dq[13] sdram bi-dir. 4 ma / 8 ma none - c11 - dq[14] sdram bi-dir. 4 ma / 8 ma none - a10 - dq[15] sdram bi-dir. 4 ma / 8 ma none - b10 - dq[16] sdram bi-dir. 4 ma / 8 ma none - c10 - dq[17] sdram bi-dir. 4 ma / 8 ma none - a9 - dq[18] sdram bi-dir. 4 ma / 8 ma none - b9 - dq[19] sdram bi-dir. 4 ma / 8 ma none - a8 - dq[20] sdram bi-dir. 4 ma / 8 ma none - b8 - dq[21] sdram bi-dir. 4 ma / 8 ma none - a7 - dq[22] sdram bi-dir. 4 ma / 8 ma none - b7 - dq[23] sdram bi-dir. 4 ma / 8 ma none - c7 - dq[24] sdram bi-dir. 4 ma / 8 ma none - b5 - dq[25] sdram bi-dir. 4 ma / 8 ma none - c5 - free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 56/69 pin name power domain pad type default pu/pd CV2201 ball cv2202 ball cv2203 ball dq[26] sdram bi-dir. 4 ma / 8 ma none - a4 - dq[27] sdram bi-dir. 4 ma / 8 ma none - b4 - dq[28] sdram bi-dir. 4 ma / 8 ma none - c4 - dq[29] sdram bi-dir. 4 ma / 8 ma none - a3 - dq[30] sdram bi-dir. 4 ma / 8 ma none - b3 - dq[31] sdram bi-dir. 4 ma / 8 ma none - c3 - system signals & jtag clkin osc oscillator pad n.a. h16 m18 k14 clkout osc oscillator pad n.a. j16 l18 j14 resetn hpi input none h11 k14 h12 hw_deep_secure dip input none p13 t16 - rtck miscif output 4 ma / 8 ma none a3 a1 a3 tck miscif input pu a4 a2 a2 ntrst miscif input pd b5 b1 a1 tdi miscif input pu b6 b2 b3 tdo miscif output 4 ma / 8 ma none b3 c1 b2 tms miscif input pu b4 c2 b1 testmode miscif input pd a1 e1 p11 pkg_opt0 (2) sdram input none - t14 - pkg_opt1 (2) sdram input none - u14 - pkg_opt2 (2) sdram input none - v14 - jtag_sel_p0 (2) miscif input none - d3 - jtag_sel_p1 (2) miscif input none - d2 - jtag_sel_p2 (2) miscif input none - d1 - no connects nc - - - a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, m7, n7, p5, p6, p7, p8, p9, r4, r5, r6, r7, r8, r9, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, a16, b16, b15, b14, b12, c16, b13, c13, u13,t13, a18, a17, b18, b17, c17, d18, c18, d15, e18, e17, e16, e15, e14, e13, f16 n10, l11, m11, n11, n12, m12, l12, l14, a10, a11, a12, a13, b11, b12, a14, c11, c12, c13, c14, d11, d12, d13, d14 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 57/69 pin name power domain pad type default pu/pd CV2201 ball cv2202 ball cv2203 ball d16, d15, d14, d13, e16, e15, e14 reserved pins reserved_1 hpi bi-dir. 2 ma / 4 ma none c14 d16 b14 reserved_2 hpi bi-dir. 2 ma / 4 ma pd c15 d17 b13 reserved_3 hpi bi-dir. 2 ma / 4 ma none g11 j14 h11 reserved_4 hpi bi-dir. 2 ma / 4 ma none h13 k16 g12 reserved_5 hpi bi-dir. 2 ma / 4 ma none g12 j15 g13 reserved_6 hpi bi-dir. 2 ma / 4 ma none h12 k15 g14 reserved_7 hpi bi-dir. 4 ma / 8 ma none g14 h14 f14 reserved_8 hpi bi-dir. 4 ma / 8 ma none g15 h15 f13 reserved_9 hpi bi-dir. 4 ma / 8 ma none g16 h16 f12 reserved_10 hpi bi-dir. 4 ma / 8 ma none f13 g14 f11 reserved_11 hpi bi-dir. 4 ma / 8 ma none f14 g15 e14 reserved_12 hpi bi-dir. 4 ma / 8 ma none f15 g16 e13 reserved_13 hpi bi-dir. 4 ma / 8 ma none f16 f14 e12 reserved_14 hpi bi-dir. 4 ma / 8 ma none e13 f15 e11 reserved_15 hpi bi-dir. 2 ma / 4 ma none g13 j16 g11 reserved_16 nand input none - - k12 reserved_17 dip bi-dir. 4 ma / 8 ma none - - p13 reserved_18 dip bi-dir. 4 ma / 8 ma none - - p12 reserved_19 nand bi-dir. 2 ma / 4 ma pu - - n4 reserved_20 nand bi-dir. 2 ma / 4 ma pu - - p4 reserved_21 nand bi-dir. 2 ma / 4 ma pu - - n5 reserved_22 nand bi-dir. 2 ma / 4 ma pu - - p5 reserved_23 dip bi-dir. 4 ma / 8 ma none - - n14 reserved_24 dip bi-dir. 4 ma / 8 ma none - - m14 reserved_25 nand bi-dir. 2 ma / 4 ma none - - p6 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 58/69 pin name power domain pad type default pu/pd CV2201 ball cv2202 ball cv2203 ball reserved_26 dip bi-dir. 4 ma / 8 ma none - - p14 reserved_27 dip bi-dir. 4 ma / 8 ma none - - l13 reserved_28 dip bi-dir. 4 ma / 8 ma none - - m13 reserved_29 dip bi-dir. 4 ma / 8 ma none - - n13 notes: (1) cv2203 does not include a display interface; ?dip_d[0 :7]? pins are used only for sampling when reset is de- asserted for determining device configuration. (2) software queries the cv2202 pkg_opt[2:0] and jtag_sel_p[ 2:0] pins to determine the sdram used in the system. currently cognivue supports a 128mb mi cron mobile ddr sdram, and the pkg_opt[2:0] and jtag_sel_p[2:0] must both be set to binary ?101? (decimal value 5). consult the factory for interfacing to any other memory. table 4-1: cv220x pinout power pin name description CV2201 ball # cv2202 ball # cv2203 ball # vdd_core core supply g8, g9, h8, h9 j8, j10, k9, l8, l10 f6, f7, f8, h6, h7, h8 vdd_lp low-power audio/video supply j7, j10, k11, k12, p14 h9, k7, k11, m9, j12, l12, t15 e9, g9, j9, k10, p10 vdda_pll analog pll supply j14 f18, g18, h18, j18, k18 h13 vssa_pll return for pll vdd ( do not connect to ground ) h14 f17, g17, h17, j17, k17 h14 vdd_sdram sdram core and ebi/sdram io supply f7,l7 g7, g8, p7, p8 d6, d8, k6, k8 vdd_osc analog supply for crystal pad j15 m17 j13 vdd_usb analog supply for usb k2 m3 k2 vddl_usb usb core supply - m5 - vdda_dac analog supply for internal dac p1 p2 p1 vdd_sensor sensor and i2c io supply f10 g10 d10 vdd_gpio gpio and keyscan supply d12 g12 - vdd_dip dip io supply l10 h12 - vdd_miscif mp2ts, jtag, spi, uart io supply d5 e5 - vdd_sdmmc sd/mmc io supply f4 g5 - vdd_audio audio io supply k9 m12 - vdd_sccard smart card power supply g5 k5 - vdd_io mp2ts, jtag, spi, uart, sdmmc, sccard, gpio/keyscan io supply - - e5, f10, g5, j5 free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 59/69 power pin name description CV2201 ball # cv2202 ball # cv2203 ball # vdd_nand nand flash io supply l4 p5 m5, h10 vss common ground c11, c12, d6, d11, f8, f9, g4, g6, h7, h10, j8, j9, j11, j12, k6, k8, l8, l9, m4, r3 d5, f5, g9, g11, h7, h8, h10, h11, j7, j9, j11, k8, k10, k12, l4, l5, l7, l9, l11, m7, m8, m10, m11, p6, r6, r7, r8 c10, d5, d7, d9, e6, e7, e8, e10, f5, f9, g6, g7, g8, g10, h5, h9, j6, j7, j8, j10, j11, j12, k7, k9, k11, l5, l6, l7, l8, l9, m4, m6, m7, n6, n7, p7 vss_dac analog ground for internal dac n1 p1, r2 m1, m2, m3 vss_usb analog ground for usb j2 m4 l2 vssl_usb usb core ground - n4, n5 - vss_osc analog ground for crystal pad h15 l17 k13 table 4-2: cv220x power pin free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 60/69 5 electrical specifications 5.1 absolute maximum rating the following table describes the absol ute maximum ratings for the cv220x. item rating unit i/o supply voltage -0.2 to +3.3 v core supply voltage -0.2 to +1.2 v input voltage for a signal pin -0.3 to +3.3 v storage temperature -40 to +85 c short circuit duration (single output in high state to gnd) 1 second table 5-1: cv220x absolute maximum rating ! warning: permanent device damage may occur if the absolute maximum ratings are exceeded. functional oper ation should be restricted to the conditions as detailed in the operati onal sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.2 recommended operating ranges the following table describes the recommended operating r anges for the cv220x. note that io_vdd refers to the subset of power supplies for the device i/os as specified in table 4-2. these supplies must be powered up before vdd_core is powered up . item symbol min. typ. max. unit core supply voltage low power audio/video voltage vdd_core vdd_lp 0.9 1.0 1.1 v io_vdd3.0 2.7 3.0 3.3 v io_vdd2.8 2.52 2.8 3.08 v i/o supply voltage io_vdd1.8 1.62 1.8 1.98 v analog pll supply vdda _pll 2.7 3.0 3.3 v sdram memory supply vdd_sdram 1.7 1.8 1.98 v voltage supply for crystal pad vdd_osc 2.52 2.8 3.08 v analog supply for usb vdd_usb 3.0 3.3 3.6 v analog supply for internal da c vdda_dac 2.97 3.3 3.63 v free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 61/69 item symbol min. typ. max. unit t operating (industrial qualified parts) -40 85 c operating temperature t operating (automotive qualified parts) -40 125 c notes: 1. io_vdd = vdd_gpio, vdd_dip, vdd_audio, vdd_ nand, vdd_sensor, vdd_sdmmc, vdd_miscif, vdd_sccard, vdd_io 2 .io_vdd must always be on. 3. vdda_pll, vdd_lp must always be on. 4. vdd_dac and vdd_usb must be turned on/o ff when vdd_core supply is turned on/off. table 5-2: cv220x recommended operating range 5.3 dc characteristics the following table describes the dc characteristics of the cv220x. item symbol min. typ. max. unit power dissipation a p stand-by tbd mw v ih 3.0 2 3.3 v v ih 2.8 1.7 3.1 v input voltage, high v ih 1.8 1.17 2.1 v v il 3.0 -0.3 0.8 v v il 2.8 -0.3 0.7 v input voltage, low v l 1.8 -0.3 0.63 v output voltage, high v oh io_vdd * 0.8 v output voltage, low v ol 0.4 v i oh_2ma 2.2 6.1 11.9 ma i oh_4ma 5.1 14.4 27.8 ma output current high (vdd=3.0v) i oh_8ma 7.3 20.5 39.6 ma i oh_2ma 4.6 8.6 14.2 ma i oh_4ma 10.7 20.2 33.1 ma output current high (vdd=2.8v) i oh_8ma 15.3 28.9 47.4 ma i oh_2ma 1.1 2.5 4.9 ma output current high (vdd=1.8v) i oh_4ma 2.5 5.9 11.5 ma free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 62/69 item symbol min. typ. max. unit i oh_8ma 3.6 8.5 16.5 ma i ol_2ma 2.8 5 7.8 ma i ol_4ma 5.6 9.5 15.5 ma output current low (vdd=3.0v) i ol_8ma 8.4 15 23.5 ma i ol_2ma 3.9 7 11 ma i ol_4ma 7.8 13.9 21.9 ma output current low (vdd=2.8v) i ol_8ma 11.8 21.1 33.2 ma i ol_2ma 1.4 2.8 4.8 ma i ol_4ma 2.9 5.6 9.6 ma output current low (vdd=1.8v) i ol_8ma 4.4 8.4 14.5 ma input capacitance c i 4 pf a. active standby power measurements are determined based on the following: code is loaded and running, processor and memory are active (ie. memory is not in self-refresh mode), arm is in low power idle mode waiting for an event to wake it up an d process something, and vdd_core is off. table 5-3: cv220x dc characteristics 5.4 ac specifications the following table provides the cv 220x external interface timing. figure 21 to figure 32 illustrate specific waveforms for each interface. parameter symbol min. typ. max. unit reset pulse width t1 1 usec input clock period t2 10 30 mhz input clock rise time t3 4 nsec input clock fall time t4 4 nsec input clock duty cycle 40 50 60 % sensor pixel clock period t5 6.25 nsec t6(2.8v) 4.35 nsec sensor input setup time t6(1.8v) 4.15 nsec sensor input hold time t7 0 nsec dip port pixel clock frequency t8 70 mhz t9 (2.8v) 7.4 nsec dip port input setup time t9 (1.8v) 9.2 nsec free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 63/69 parameter symbol min. typ. max. unit dip port input hold time t10 0 nsec t11 (2.8v) 5.5 nsec dip port output delay time t11 (1.8v) 5.1 nsec dip port output hold time t12 0 nsec spi port clock frequency (master) t13 30 mhz t14 (2.8v) 8.3 nsec spi port input setup time (master) t14 (1.8v) 11.5 nsec t15 (2.8v) 6.3 nsec spi port output delay time (master) t15 (1.8v) 6.5 nsec spi port clock frequency (slave) t13 30 mhz t14 (2.8v) 5.3 nsec spi port input setup time (slave) t14 (1.8v) 5.2 nsec t15 (2.8v) 8.3 nsec spi port output delay time (slave) t15 (1.8v) 11.2 nsec audio_clk frequency t22 50 mhz t23(2.8v) 6.7 nsec input data (audio_fs, audi o_dr) setup time to the rising edge of audio_clk t23(1.8v) 6.8 nsec input data (audio_fs, audi o_dr) hold time from the rising edge of audio_clk t24 0 nsec t25 (2.8v) 12.4 nsec output data (audio_fs, audio_dx) delay time from the rising edge of audio_clk t25 (1.8v) 15.6 nsec output data (audio_fs, audio_dx) hold time from the rising edge of audio_clk t26 0 nsec mmc port clock frequency t27 25 mhz t28 (2.8v) 1.8 nsec mmc port input setup time t28 (1.8v) 4.6 nsec mmc port input hold time t29 0 nsec t30 (2.8v) 9.9 nsec mmc port output delay time t30 (1.8v) 8.3 nsec mp2ts interface clock frequency t31 30 mhz t32(2.8v) 4.7 nsec mp2ts interface input setup time t32(1.8v) 4.5 nsec mp2ts interface input hold time t33 0 nsec i2c port clock frequency t34 10 mhz i2c port input setup time t35 15 nsec free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 64/69 parameter symbol min. typ. max. unit i2c port input hold time t36 0 nsec i2c port output delay time t37 15 nsec i2c port output hold time t38 0 nsec mmcplus port clock frequency t39 52 mhz mmcplus port input hold time t40 5 nsec t41 (2.8v) 3.5 nsec mmcplus port input setup time t41 (1.8v) 6.6 nsec mmcplus port output hold time t42 3 nsec t43 (2.8v) 16.5 nsec mmcplus port output delay time t43 (1.8v) 16.7 nsec gps clock period t44 20 mhz t45(2.8v) 5.1 nsec gps setup time t45(1.8v) 5 nsec gps hold time t46 0 nsec pmi clock frequency t47 15 mhz pmi input setup time t48 7 nsec pmi input hold time t49 26 nsec pmi output delay time t50 18 nsec table 5-4: cv220x ac specifications power supply resetn t1 pll locked internal reset 0.5 msec free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 65/69 figure 21: reset timing clkin t2 t3 t4 figure 22: input clock timing sensor_pclk t5 t6 t7 inputs figure 23: sensor interface timing dip_pclk t8 t9 t10 inputs t11 outputs t12 figure 24: dip port timing free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 66/69 spi_clk t13 t14 inputs t15 outputs figure 25: spi port timing t23 audio_clk audio_fs audio_dr audio_dx t24 t26 t25 t22 figure 26: audio port timing free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 67/69 t28 inputs t30 outputs t27 sd_clk t29 figure 27: sd/mmc port timing t32 t33 inputs t31 mp2ts_clk figure 28: mp2ts interface timing t35 t36 sda (in) t37 sda (out) t34 scl t38 figure 29: i2c port timing free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 68/69 t42 inputs t39 outputs t40 nand_cen[0] (mmcplus_clk) t41 t43 figure 30: mmcplus port timing gps_clk t44 t45 t46 inputs figure 31: gps interface timing t48 t49 pmi_ data_in pmi_ data_out t47 pmi_clk t50 figure 32: pmi port timing free datasheet http:///
ds-10163-00-01 cognivue confidential and proprietary 69/69 6 ordering information part numbers for the cv220x fa mily of processors are: CV2201-350cbi cv2202-350cbi cv2203-350cbi cv2203-350cba free datasheet http:///

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